Lam Research and imec have extended their strategic collaboration to advance next-generation 3D integration and Aether dry resist for high-NA extreme ultraviolet (EUV) patterning. This joint research aims to enable future artificial intelligence (AI) logic, memory, and heterogeneous integration technologies.AI models demand unprecedented computing power, memory bandwidth, and energy efficiency, the companies said. Meeting these requirements increasingly depends on how chips are designed, connected, packaged, and manufactured as complete systems.Three-dimensional integration, advanced packaging, next-generation memory, and new patterning technologies are critical enablers for AI computing. These allow chipmakers to overcome traditional scaling constraints and deliver necessary performance gains.Lam and imec are collaborating to accelerate manufacturing readiness for 3D integration technologies. This supports advanced packaging and next-generation memory architectures.The collaboration combines Lam’s deposition and etch capabilities with imec’s integration infrastructure. This aims to boost the speed at which innovations move from lab to high-volume manufacturing.Joint research areas include thick dielectric deposition, asymmetric stress compensation, bevel deposition, and plasma dicing. The work also covers process validation for advanced packaging and future memory architectures.It extends into future 3D memory technologies, such as new charge-trap materials and precision multilayer deposition. High-aspect-ratio channel etch, deep memory contacts, and low-resistivity interconnects are also part of the focus.These innovations are crucial as AI workloads drive demand for greater memory density and bandwidth.
Advancing High-NA EUV Patterning
AI also relies on continued advances in leading-edge logic devices, the companies noted. High-NA EUV lithography is required to enable smaller features and increased transistor density for angstrom-era nodes.Lam and imec are advancing the application of Lam’s Aether dry resist platform for high-NA EUV patterning. This joint work uses imec’s high-NA EUV research environment.The focus is on enhancing resolution, sensitivity, depth of focus, and stochastic defectivity. The collaboration explores Aether-enabled patterning for advanced interconnects, including ruthenium direct metal etch.These innovations support lower-resistivity interconnects and improved electrical performance for future logic nodes. Joint research achieved single-exposure high-NA EUV patterning for sub-20 nm ruthenium direct metal etch interconnects.This work obtained 100 per cent electrical yield for fork structures sensitive to bridges. It also achieved over 90 per cent for meander structures sensitive to breaks at 20 nm pitch.Aether-enabled patterning could reduce multi-patterning complexity and improve manufacturability. Aether is part of a broader approach to enabling gate-all-around (GAA) and complementary FET (CFET) architectures for future AI computing.