Copper has wired semiconductor chips since the late 1990s, but its reign over the narrowest metal lines in advanced logic is ending — and a demonstration published this week by Lam Research and Belgian research institute imec shows exactly what comes next. Working inside imec’s high-NA EUV research environment in Leuven, Belgium, the joint team has achieved 100% electrical yield for ruthenium direct metal etch structures at 20nm pitch using a single high-NA extreme ultraviolet (EUV) exposure — a result that validates Lam’s Aether dry resist platform as a manufacturable solution for the angstrom-era chips that AI infrastructure increasingly demands.
The Lam Research’s October announcement, posted to Lam Research’s newsroom on October 27, also expands the long-standing collaboration between Lam and imec into two new research domains: enabling advanced 3D integration and next-generation memory architectures, and advancing the Aether dry resist platform for high-NA EUV patterning. Together, they represent Lam’s most comprehensive public commitment yet to the process stack required for chips below the 2nm node.
Why Copper Cannot Wire Angstrom-Era Chips
To understand what Lam and imec demonstrated, it helps to understand what they were solving for. Copper has been the industry’s interconnect material of choice because of its low bulk electrical resistance. But that advantage disappears sharply once interconnect line widths fall below roughly 10nm, a threshold the industry’s most advanced nodes are now crossing.
At narrow dimensions, copper suffers from two compounding problems. First, the mean free path of electrons in copper is approximately 40nm — longer than the feature itself at advanced nodes — which causes resistance to spike as electrons scatter off grain boundaries and sidewalls. Second, copper requires a diffusion barrier layer (typically tantalum nitride) to prevent it from migrating into adjacent dielectric. At sub-10nm line widths, that barrier consumes so much of the conductor’s cross-section that the effective copper volume — and thus its conductance — collapses.
Ruthenium offers a different physics. Its electron mean free path is approximately 6.7nm, far shorter than copper’s, which means its sub-10nm resistivity advantage scales more gracefully at small dimensions. Research from KU Leuven and confirmed by multiple IEEE International Interconnect Technology Conference studies through 2025 shows that for sub-10nm upper metal lines, KU Leuven crossover research confirms ruthenium, rhodium, and iridium maintain lower effective resistivity than copper. Ruthenium also eliminates the need for a separate diffusion barrier, recovering the conductor cross-section that copper’s liner requirements waste.
That physics is driving the semiconductor industry’s push toward ruthenium for the narrowest metal layers in advanced logic nodes — but ruthenium requires a different patterning approach than copper’s traditional dual-damascene integration scheme. This is where dry resist and direct metal etch become critical.
What Dry Resist Is and Why High-NA EUV Needs It
For most of the history of chip manufacturing, photoresists have been wet: liquid polymers spin-coated onto a wafer, exposed to light, and then chemically developed in a solvent bath. That approach worked well for decades, but at the pitches required for high-NA EUV — the next generation of extreme ultraviolet lithography, which uses a 0.55 numerical aperture rather than the 0.33 NA of current production tools — conventional wet resists face mounting structural problems.
The most severe is stochastic defectivity. At sub-20nm pitches, random variations in the distribution of photons and resist molecules create feature-to-feature inconsistencies — microbridges between lines that should be separate (shorts), and line pinches where a feature narrows to a break (opens). Chris Mack, CTO of Fractilia, has noted that stochastic defects consume half the budget in advanced EUV patterning, consuming as much as half the edge placement error budget. High-NA EUV makes this worse in one specific way: its tighter depth of focus requires thinner resist films, which means thinner resists capture fewer photons per exposure, potentially amplifying the stochastic variation.
Lam’s Aether dry resist addresses these problems at the process level. Rather than being spin-coated from a liquid, Aether resist is deposited via vapor deposition and plasma development — a chemical deposition process analogous to atomic layer deposition — and then developed using plasma-based dry processes rather than solvent baths. This eliminates the solvent-related failure modes: no liquid surface tension to collapse lines during drying, no thermal variation from evaporation, and no solvent chemistry that conflicts with the new interconnect materials (like ruthenium) being introduced at sub-10nm nodes. As Lam’s published platform description explains it, Aether “enables vacuum-based formation of resist underlayers and films and utilizes dry development processes to improve pattern fidelity at small pitch dimensions.”
What Lam and imec Demonstrated
The joint research team conducted its work on imec’s high-NA EUV infrastructure, which since March 2026 includes the ASML EXE:5200, one of fewer than a dozen such tools in existence worldwide and the most advanced lithography system commercially available. Details of imec’s Leuven EXE:5200 installation were confirmed in an official imec press release dated March 18, 2026. The system has an EXE:5200 full qualification by Q4 2026 target, meaning the Lam-imec Aether work is being conducted in one of the most capable, freshly commissioned research environments in the world.
The demonstration achieved:
Full electrical yield — 100% — for fork test structures at 20nm pitch using a single high-NA EUV exposure. Fork structures are sensitive to bridges, the most common stochastic failure mode for line-and-space patterns at tight pitch.
Above 90% electrical yield for meander test structures at 20nm pitch, across the full wafer. Meander structures are sensitive to breaks, the other primary stochastic failure mode.
Both results were obtained through ruthenium direct metal etch — meaning the ruthenium metal itself was patterned directly through the Aether resist, rather than through the multi-step dual-damascene sequence used for copper. The Aether dry resist yield results at 20nm pitch are consistent with the metal layers required in logic nodes below 2nm.
The significance of 100% fork yield is not incremental. In production semiconductor manufacturing, a bridge in any fork structure is a short-circuit failure. Achieving zero bridges across an entire wafer at this pitch — on a new interconnect metal, using a new resist technology, in a single exposure without multi-patterning — demonstrates that the Aether/ruthenium combination meets the primary stochastic yield bar for this generation of devices.
Why This Result Matters Now
The Lam/imec demonstration lands at a specific moment in the industry’s transition to high-NA EUV. ASML CEO’s HVM timeline statement confirms high-volume manufacturing with high-NA tools is expected to begin in 2027 and 2028, with 2026 serving as the critical year for qualifying machines and building process confidence across the ecosystem. That transition is already under way at leading chipmakers.
Intel has been the most aggressive adopter, with Intel’s one million wafers milestone now surpassed — more than one million wafers processed through its high-NA EUV systems — with Intel Foundry entering high-volume manufacturing for Core Ultra Series 3 (Panther Lake) processors using selected Intel 18A layers patterned on high-NA EUV tools. SK Hynix became the first chipmaker to install a commercial high-NA EUV system in a production environment, in late 2025. TSMC has since committed to adopting high-NA EUV for high-volume manufacturing in 2030, a shift that underscores the tool’s position as central to the industry’s long-term roadmap — even as the high-NA EUV tool cost range of approximately $350 to $400 million per unit remains a significant adoption threshold.
For Lam, the timing of the imec collaboration is deliberate. The company has spent the past 14 months assembling a dry resist ecosystem ahead of wider high-NA EUV adoption. In January 2025, Lam announced that Aether had been selected as the Aether platform’s DRAM selection as production tool of record for advanced DRAM by a leading memory manufacturer. In September 2025, Lam signed a JSR Inpria cross-licensing agreement with JSR Corporation and its subsidiary Inpria, integrating JSR’s metal-oxide resists with Lam’s etch, deposition, and dry resist capabilities for high-NA EUV applications. In March 2026, IBM and Lam announced a IBM Lam sub-1nm collaboration five-year collaboration targeting sub-1nm logic using high-NA EUV and Aether dry resist at IBM’s Albany NanoTech Complex. The imec expanded partnership announced on October 27 is the latest move in that sequence.
3D Integration: The Other Dimension of the Collaboration
While the Aether patterning milestone has the clearest technical headline, the 3D integration scope of the expanded Lam-imec collaboration may have equal long-term significance for the industry’s AI infrastructure roadmap.
Training and deploying large AI models requires not just faster logic but dramatically more memory bandwidth, tighter chip-to-chip interconnects, and substantially better energy efficiency per computation. Transistor scaling alone cannot deliver all three simultaneously, which is why heterogeneous integration — combining logic, memory, and I/O chiplets into unified systems — has become a structural pillar of AI chip design. The AI-driven demand for high-bandwidth memory (HBM) is the most visible current expression of this trend, but its process requirements are far more demanding.
The Lam-imec 3D integration work targets the specific manufacturing hurdles that separate laboratory demonstrations from high-volume production. These include thick dielectric deposition (which must maintain uniformity across complex stacked structures), asymmetric stress compensation (critical for managing wafer bow when depositing layers with mismatched thermal expansion), bevel deposition (required for edge passivation in stacked device architectures), and plasma dicing (which replaces mechanical dicing to reduce kerf width and die stress). On the memory side, the joint research addresses new charge-trap materials, precision multilayer deposition, high-aspect-ratio channel etch (required for stacking hundreds of memory layers), deep memory contacts, and low-resistivity interconnects — essentially the full process stack that next-generation DRAM and 3D NAND architectures require.
The rationale for tackling these challenges at imec specifically is structural. The NanoIC pilot line public funding — a €2.5 billion (approximately $2.75 billion) investment, of which €1.4 billion (approximately $1.54 billion) comes from public sources including the EU Chips Act — provides the most advanced shared-access fabrication infrastructure available outside a major chipmaker’s own fab. That infrastructure — combined with imec’s role as a neutral party that serves ASML, Applied Materials, Tokyo Electron, and Lam simultaneously — makes it uniquely positioned to validate multi-vendor process flows before any single chipmaker commits to them at production scale.
What Comes Next for Angstrom-Era Chips
Lam’s Aether platform sits alongside its Akara etch systems and Striker ALD portfolio as part of the equipment set the company believes will define the process flows for gate-all-around (GAA) and complementary FET (CFET) transistor architectures — the successors to today’s FinFET designs expected to power chips below the 2nm node. Both GAA and CFET require precise deposition and etch control at the device level, and both depend on patterning technologies that can define features at the pitches where ruthenium becomes the preferred interconnect material.
The Lam-imec collaboration is structured as a research partnership, not a product launch. Neither company has disclosed a timeline for when specific joint findings will translate into commercial processes at customer foundries. That is consistent with how the semiconductor equipment industry typically works: establish feasibility in a shared research environment, refine process parameters at scale, then transfer to production fabs over a cycle of several years. The 2027–2028 high-NA EUV high-volume manufacturing window that ASML has indicated is the target horizon for these results to become practically relevant.
Anand Murthy, Lam’s Vice President of Advanced Technology Integration, authored the October 27 announcement — a signal that the collaboration sits at Lam’s strategic core, not at its periphery. For imec, the Lam partnership deepens the ecosystem surrounding its high-NA EUV infrastructure at a moment when that infrastructure is becoming one of the most strategically important research environments in the semiconductor world. With ASML, Intel, SK Hynix, IBM, and now Lam conducting work within or alongside imec’s facilities, the Belgian research center is cementing its role as the industry’s de facto advanced-node laboratory — the place where angstrom-era manufacturing will first be made real.
Exchange rate as of October 28, 2026; conversions are approximate.
Frequently Asked Questions
What exactly did Lam Research and imec demonstrate, and why does it matter?
The joint research team used Lam’s Aether dry resist and a single high-NA EUV exposure to pattern ruthenium metal lines at 20nm pitch, achieving 100% electrical yield for fork test structures (sensitive to short circuits) and above 90% for meander structures (sensitive to line breaks) across the full wafer. This matters because it validates two simultaneous transitions the semiconductor industry must make: moving from copper to ruthenium as the interconnect metal of choice for the narrowest lines in advanced chips, and moving from liquid wet resists to vapor-deposited dry resists to control the stochastic defects that undermine yield at these dimensions. Clearing both transitions in a single-exposure process, in imec’s high-NA EUV environment, represents a meaningful step toward manufacturable angstrom-era logic.
What is high-NA EUV and how is it different from current chipmaking tools?
EUV lithography uses 13.5nm extreme ultraviolet light to print circuit patterns onto silicon wafers. Current production EUV tools have a numerical aperture of 0.33, which limits the finest features they can print in a single exposure. High-NA EUV scanners — specifically ASML’s 0.55 NA resolution advantage in the EXE:5200 — use a numerical aperture of 0.55, enabling circuit features up to approximately 66% smaller. That improvement is necessary for the sub-2nm logic nodes and high-bandwidth memory architectures that AI accelerators will require starting around 2027 and 2028, but it also demands new resists (because the tool’s reduced depth of focus requires thinner films) and new interconnect metals (because copper’s resistance becomes prohibitive at the dimensions high-NA EUV enables).
Why is dry resist better than conventional wet resist for high-NA EUV patterning?
Conventional wet photoresists are spin-coated onto wafers from liquid solutions and developed using liquid solvents after EUV exposure. At sub-20nm pitches, this creates two categories of problems: stochastic defects from random variations in photon absorption and resist molecule distribution, and physical failures during liquid development where surface tension causes narrow features to collapse before they can be cured. Dry resist — like Lam’s Aether, deposited via vapor-phase precursors and developed using plasma-based processes — eliminates the liquid phase entirely, removing both failure modes at their root. It also avoids the solvent compatibility issues that arise when patterning ruthenium, which is not processed through the same chemistry as copper. The dry versus wet resist tradeoffs in EUV patterning are described extensively in the semiconductor engineering literature; the Lam/imec result demonstrates that dry resist resolves them in practice at production-relevant pitch.
When will high-NA EUV chips reach consumers?
The first product-oriented high-NA EUV wafers are already flowing through Intel’s systems, targeting Core Ultra Series 3 (Panther Lake) laptop processors — Intel Foundry entered high-volume manufacturing for selected Intel 18A layers using high-NA EUV tools as of July 2026. Fouquet’s first products timeline at imec’s ITF World 2026 conference in May indicated the first chip products manufactured on high-NA tools were expected within months, and imec’s EXE:5200 in Leuven is targeted for full qualification by the fourth quarter of 2026. Broad high-volume manufacturing across multiple chipmakers — including TSMC, which has committed to high-NA EUV from 2030 — is expected in 2027 and 2028. The process research being done now at imec — including the Lam Aether and 3D integration work — is the qualification work that must succeed before those manufacturing timelines can be met.